Various reasons indicating such a combination would be in demand include:
- Power usage
Since the ClearSpeed boards have approximate power consumption of 25-33 Watts (depending on model), adding two of the PCIe-8x boards to a a T5220 would only increase power usage by 66W with an aggregate 133 GFLOPS increase in computing power. Sun obviously believes stuffing ClearSpeed boards into their servers are a valid play:TIT'sTokyo Tech's TSUBAME cluster achieved a 24% speedup for a 1% increase in power usage. - Floating Point performance
Real World Tech's excellent article posits that the floating-point ratio in the instruction mix on the first Niagara iteration could exceed no more than 1%-3%. Clearly, the demand for floating point was sufficient to increase the resources dedicated to it from 1 FP unit per chip, up to 1 FP unit per core. Presumably further FP acceleration would be even more beneficial.
No comments:
Post a Comment